SPLVM Virtualized System Meetup

Host: Mossaka

  1. Community hosted meetup for discussing anything related to distributed systems, operating systems, database, and networking. Currently focusing on virtualization, tracking course UCSD CSE 291.
  2. Schedule
  3. Biweekly Zoom meeting on Monday at 5pm PDT
  4. Code of Conduct
  5. Please use “Raise Hands” feature on Zoom
  6. Welcome to unmute or comment in chat at ANY TIME!

Background

https://stackoverflow.com/questions/37825859/cache-miss-a-tlb-miss-and-page-fault

https://stackoverflow.com/questions/37825859/cache-miss-a-tlb-miss-and-page-fault

The CPU generates the page number and page offset

Page Table maps page number to page frame number

page frame number + page offset → physical memory

  1. lookup page number in TLB
    1. TLB miss: go to Page Table
    2. TLB hit: we find page frame number and don’t go Page Table
  2. Page Fault
    1. occurs when the page accessed by a running program is not present in physical memory. It means the page is present in secondary memory but not yet loaded into a frame of physical memory
    2. use page replacement algorithm if page table is full

Software-controlled TLB

  1. on a TLB hits, MMU checks the valid bit
    1. if valid, perform addr translation
    2. if invalid, generates a page fault
  2. on a TLB miss, HW raises exception, traps into the OS and OS parses page table loads PTE into TLB

Hardware-controlled TLB

  1. on a TLB hits, MMU checks the valid bit
    1. if valid, perform addr translation
    2. if invalid, generates a page fault
  2. on a TLB miss, MMU parses page table loads PTE into TLB